What is Verilog?

 Keywords: Verilog

 

What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

What are HDLs?

An HDL provides the framework for the complete logical design of the ASIC.  Verilog and VHDL are the two most commonly used HDLs today. Both have constructs with which the design can be fully described at all the levels. There are additional constructs available to facilitate setting up of the test bench, spelling out test vectors for them and “observing” the outputs from the designed unit.

Verilog as an HDL

Verilog has a variety of constructs as part of it. All are aimed at providing a functionally tested and a verified design description for the target FPGA or ASIC. The language has a dual function – one fulfilling the need for a design description and the other fulfilling the need for verifying the design for functionality and timing constraints like propagation delay, critical path delay, slack, setup, and hold times. One major difference from a language like ‘C’ is that Verilog allows processes to run in parallel. This is obviously very desirable if one is to describe the behaviour of hardware in a realistic way.

Verilog is a case-sensitive language like C. Thus sense, Sense, SENSE, sENse… etc., are all treated as different entities / quantities in Verilog.

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

Typical Design Flow:

Brief introduction of Verilog structure:

Verilog design consists of hierarchy or collection of design modules. These Verilog modules can communicate to each other with a set of input, output, and/or bidirectional ports. Internally, a Verilog module contains a list of wires and registers. Verilog HDL can be used to design the hardware at difference level of abstraction. Here abstraction means the level of detail of the design. The abstraction levels can be Algorithmic level, RTL level, Gate level, Switch level. Depends on the designs and needs appropriate level of abstraction is used. In general RTL level coding is widely used.

 Every Verilog module has three different blocks, port list, declaration area, main body.

• Port list comprise list of ports with that the logic can communicate to other modules / designs.
• Declaration area defines the ports as input or output and also declares internal registers, wires and constants.
• Main body, here the functionality of the circuit defined it can be structural or algorithmic or RTL type of coding.

A simple Verilog Example

// A simple example                 ---           comment line

module and2 (a, b, c);            ---           module name (port list)

input a, b;                                ---           port declarations

output c;                                  ---           port declarations

assign c = a & b;                     ---           body

endmodule                               ---           end module

// A simple example                 ---           comment line

Modules:

A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designer to modify module internals without affecting the rest of the design.

Any Verilog program begins with a keyword – called a “module.” A module is the name given to any system considering it as a black box with input and output terminals.

Ports:

The terminals of the module are referred to as ‘ports’. Ports allow communication between a module and its environment. The ports attached to a module can be of three types:

input ports: through which one gets entry into the module; they signify the input signal terminals of the module.

output ports: through which one exits the module; these signify the output signal terminals of the module.

inout ports: These represent ports through which one gets entry into the module or exits the module; These are terminals through which signals are input to the module sometimes; at some other times signals are output from the module through these.