Verilog Code For Half Adder and Full Adder

Verilog Code For Half Adder and Full Adder:

 

Half Adder Using Data Flow:

module ha ( a, b, s, c)

input a, b;

output s, c;

assign s= a ^ b;

assign c= a & b;

endmodule

Half_adder using Structural:

----------------------------- XOR ------------------------------------------------------

module xor1(s, a, b);

    output s;

    input a, b;

    assign s= a ^ b;

endmodule

------------------------------AND--------------------------------------------------------

module and1(s, a, b);

    output s;

    input a, b;

    assign c= a & b;

endmodule

----------------------Half Adder---------------------------------------------------

module ha(s, c, a, b);

    output s, c;

    input a, b;

    xor1 u1(s, a, b);

    and1 u2 (c, a, b);

endmodule

Full adder using data flow model:

module full_adder (a, b, cin, sum, cout);

input a, b, cin;

output sum, cout;

assign sum=a ^ b ^ cin;

assign cout=( a & b ) | ( b & cin ) | ( cin & a );

endmodule

Full adder using Behavioral Model:

module full_adder1  (a, b, cin, sum, cout);

input a, b, cin;

output reg sum, cout;

reg T1,T2,T3,S1;

always@(a, b, cin)

begin
T1 = a & b;

T2 = b & cin;

T3 = cin & a ;

Cout = T1 | T2 | T3;

S1 = a ^ b;

Sum = S1 ^ cin;

end
endmodule

Full adder using structural modeling (using two half adders and one or gate)

---------------------------- Half Adder ------------------------------------------------

module halfadder (a, b, s, c);

input a, b;

output s, c;

assign s=a ^ b;

assign c=a & b;

endmodule

-------------------------Full Adder-----------------------------------------------------
module full_adder_structural (a, b, cin, sum, cout);

input a, b, cin;

output sum, cout;

wire c1,c2,s1;

halfadder u1(a,b,s1,c1);

halfadder u2 (s1,cin,sum,c2);

or (cout, c1, c2);

endmodule