VHDL Code for All Logic Gates
1. AND Gate:
TRUTH TABLE:
x y z
0 0 0
0 1 0
1 0 0
1 1 1
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is
port( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC );
end AND2;
--Dataflow model
architecture behav1 of AND2 is
begin
Z<= x and y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of AND2 is
begin
process (x, y)
begin
if (x='1' and y='1') then -- Compare with truth table
Z <= '1';
else
Z <= '0';
end if;
end process;
end behav2;
2. OR Gate
TRUTH TABLE:
x y z
0 0 0
0 1 1
1 0 1
1 1 1
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is
port(x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end OR2;
--Dataflow model
architecture behav1 of OR2 is
begin
Z <= x or y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of OR2 is
begin
process (x, y)
begin
if (x='0' and y='0') then -- Compare with truth table
Z <= '0';
else
Z<= '1';
end if;
end process;
end behav2;
3. NOT Gate:
TRUTH TABLE:
x z
0 1
1 0
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity not1 is
port(X: in STD_LOGIC;
Z: out STD_LOGIC);
end not1;
--Dataflow model
architecture behav1 of not1 is
begin
Z<= not X; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of not1 is
begin
process (X)
begin
if (x='0') then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end behav2;
4. NAND Gate
TRUTH TABLE:
x y z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity nand2 is
port(x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nand2;
--Dataflow model
architecture behav1 of nand2 is
begin
z<= x nand y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of nand2 is
begin
Process (x, y)
Begin
If (x='1' and y='1') then -- Compare with truth table
Z <= '0';
else
Z <= '1';
end if;
end process;
end behav2;
5. NOR Gate:
TRUTH TABLE:
x y z
0 0 1
0 1 0
1 0 0
1 1 0
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity nor2 is
Port (X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC);
end nor2;
--Dataflow model
architecture behav1 of nor2 is
begin
Z<= x nor y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of nor2 is
begin
process (x, y)
begin
If (x='0' and y='0') then -- Compare with truth table
Z <= '1';
else
Z <= '0';
end if;
end process;
end behav2;
6. EX-OR Gate:
TRUTH TABLE:
x y z
0 0 0
0 1 1
1 0 1
1 1 0
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor2 is
Port (X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC);
end xor2;
--Dataflow model
architecture behav1 of xor2 is
begin
Z<= x xor y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of xor2 is
begin
process (x, y)
begin
If (x/=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end behav2;
7. EX-NOR Gate:
TRUTH TABLE:
x y z
0 0 1
0 1 0
1 0 0
1 1 1
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xnor2 is
Port (X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC);
end xnor2;
--Dataflow model
architecture behav1 of xnor2 is
begin
Z<= x xnor y; --Signal Assignment Statement
end behav1;
-- Behavioral model
architecture behav2 of xnor2 is
begin
process (x, y)
begin
If (x=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end behav2;
