Addressing Modes: 8051

keywords: 8051, microcontroller

8051 Addressing Modes:

When instructions operate on data, the question arises: "Where are the data?" The answer to this question lies in the 8051's "addressing modes."   An "addressing mode" refers to how you are addressing a given memory location. The8051 instructions use eight addressing modes. These are:

1. Register 
2. Immediate
3. Direct
4. Indirect

Each of these addressing modes provides important flexibility.

 

Register Addressing:

The register banks, which contains registers R0 through R7, can be accessed by instructions whose opcodes carry a 3-bit register specification. Instructions that access the registers this way make efficient use of code, since this mode eliminates an address byte. When the instruction is executed, one of four banks is selected at execution time by the row bank select bits in PSW.

                 MOV A, Rn                   ; copy contents of Rn into A

     MOV A, #n                     ; copy the immediate data byte n to the register A.

     MOV Rn, A                    ; copy contents of A into Rn.

     MOV Rn, #n                   ; copy the immediate data byte n to the register Rn.

     MOV DPTR, #nn            ; copy the immediate 2 byte data nn to the register DPTR.

*Note: The source and destination registers must match in size.

 

Immediate Addressing:

When a source operand is a constant rather than a variable, then the constant can be incorporated into the instruction as a byte of "immediate" data. An additional instruction byte contains the value.

In assembly language, immediate operands are preceded by a number sign (#). The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constants, symbols, and operators. The assembler computes the value and substitutes the immediate data into the instruction. For example, the instruction

             MOV A, #25H;                load 25H into A

             MOV R4, #62;                 load 62 into R4

             MOV DPTR, #4521H;        DPTR=4512H

 

Direct Addressing:

It differs from register addressing in that any byte within the first 256 addresses can be accessed by specifying 8-bit address. When using this mode, there is few things watch out for. The first RAM addresses (080h to 0FFh, if the device you are using has RAM at these locations) cannot be accessed by direct memory addressing.

            MOV R0, 40H;                 save content of 40H in R0

            MOV 56H, A;                   save content of A in 56H

 

Indirect Addressing:

As the name indicates it is an indirect mode of addressing. It uses R0 or R1 as an 8-bit index register to access a byte in the first 256 addresses of the data space. The register indirect addressing mode is identified by the symbol '@' before either R0 or R1. Using any other bank (R2 to R7) will result in an error.

                             MOV     A, @R0;       move contents of RAM whose address is held by R0 into A

                             MOV     @R1, B;       move contents of B into RAM whose address is held by R1

External Data Addressing:

Pointer used for external data addressing can be either R0/R1 (256 byte access) or DPTR (64kbyte access).
For example - 

            MOVX   A, @R1;               Moves content of 8-bit address pointed by R0 to A

            MOVX   A, @DPTR;         Moves content of 16-bit address pointed by DPTR to A

External Code Addressing:

Sometimes we may want to store non-volatile data into the ROM e.g. look-up tables. Such data may require reading the code memory. This may be done as follows - 

           MOVC   A, @A+DPTR;     Moves content of address pointed by A+DPTR to A

           MOVC   A, @A+PC;          Moves content of address pointed by A+PC to A 

keywords: 8051, microcontroller

8051: Timer, Counter & Interrupts

 keywords: 8051, microcontroller

8051: Timer, Counter & Interrupts

Timers and Counters:

8051 has two 16-bit programmable UP timers /counters. They can be configured to operate either as timers or as event counters. The names of the two counters are T0 and T1 respectively.  Each counter may be programmed to count internal clock pulses, acting as a timer (or) programmed to count external pulses as a counter. The counters are divided into two 8-bit registers called the timer low (TL0, TL1) and timer high (TH0, TH1).

In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine cycles. Hence the clock rate is 1/12 ^th of the oscillator frequency.

In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 ^th of oscillator frequency.

The operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively.

SFR’S Used:

(i)                  TMOD Register

(ii)                TCON  Register

(iii)               Timer(T0) & timer(T1) Registers

TMOD (Time Mode Control) Register:

TMOD register is not bit addressable.

Various bits of TMOD are described as follows -

Gate: This is an OR Gate enabled bit which controls the effect of  on START/STOP of Timer. It is set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and signal on INT1/0  pin is high then the timer starts counting using either internal clock (timer mode) or external pulses (counter mode).

 

C /T : Set to 1 by program to make timer 1/ timer 0 act as a counter by counting pulses from external input pins 3.5 / pin 3.4. Cleared to zero by program to make timer act as a timer by counting internal frequency.

M1 - Timer/counter operating mode select bit 1. Set/cleared by program to select mode.

M0 - Timer/counter operating mode select bit 0. Set/cleared by program to select mode.

M1	M0	Mode	Operation Mode
0	0	Mode 0	13 – bit timer
0	1	Mode 1	16 – bit timer/counter
1	0	Mode2	8 – bit auto reload timer/counter
1	1	Mode 3	(Timer 0) TL0 is an 8 – bit timer/counter, controlled by the standard Timer 0 control bits.

 

TCON Register:

The timer control SFR is used to configure and modify the way in which the 8051’s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR.

These bits are used to configure the way in which the external interrupt flags are activated, which are set when an external interrupt occurs.

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1 bit is automatically set on the Timer 1 overflow.

TR1 bit enables the Timer 1.

1 - Timer 1 is enabled.

0 - Timer 1 is disabled.

TF0 bit is automatically set on the Timer 0 overflow.

TR0 bit enables the timer 0.

1 - Timer 0 is enabled.

0 - Timer 0 is disabled.

 

Timer 0 (T0):

TH0 and TL0, these two SFRs taken together represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.

TH0 Register

TL0 Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Formula used to calculate values in these two registers is very simple:

TH0 × 256 + TL0 = T

Timer 1 (T1):

TH1 and TL1, these two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is Configurable is how and when they increment in value.

TH1 Register

TL1 Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8051 Interrupts:

8051 provides 5 vectored interrupts. They are -

1. INT0
2. TF0
3. INT1
4. TF1
5. RI/TI

Out of these, INT0 and INT1 are external interrupts whereas Timer and Serial port interrupts are generated internally. The external interrupts could be negative edge triggered or low level triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the processor branches to the Interrupt Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by software by the programmer.

External Interrupts

Port P3 of 8051 is a multi-function port. Different lines of this port carry out functions which are additional to data input-output on the port. Additional functions of Port 3 lines:

 

P3.0             RXD (serial input port)

P3.1             TXD (serial output port)

P3.2        INTO (external interrupt 0)

P3.3        INT1 (external interrupt 1)

P3.4        T0   (timer 0 external input)

P3.5        T1 (timer 1 external input)

P3.6        WR (external data memory write strobe)

P3.7        RD (external data memory read strobe)

Internal Interrupts:

Internally generated interrupts can be from either timer, or from the serial interface. The serial interface causes interrupts due to a receive event (RI) or due to a transmit event (TI). The receive event occurs when the input buffer of the serial line (sbuf in) is full and a byte needs to be read from it. The transmit event indicates that a byte has been sent a new byte can be written to output buffer of the serial line (sbuf out). 8051 timers always count up. When their count rolls over from the maximum count to 0000, they set the corresponding timer flag TF1 or TF0 in TCON. Counters run only while their run flag (TR1 or TR0) is set by the user program. When the run flag is cleared, the count stops incrementing. The 8051 can be setup so that an interrupt occurs whenever TF1 or TF0 is set.

Enabling Interrupts:

At power-up, all interrupts are disabled. Suppose Timer 0 is started. When it times out, TF0 in the special function register TCON will be set. However, this will not cause an interrupt. To enable interrupts, a number of steps need to be taken. Interrupts are enabled in a manner which is quite similar to the 8085. There is an interrupt enable special function register IE at byte address A8H. This register is bit addressable.

Interrupt Enable register (IE):

               

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
EA	--	ET2	ES	ET1	EX1	ET0	EX0

EX0:           interrupt (External)   enable bit

ET0:           Timer-0 interrupt enable bit

EX1:           interrupt (External) enable bit

ET1:           Timer-1 interrupt enable bit

ES:             Serial port interrupt enable bit

ET2:          Timer-2 interrupt enable bit

EA:            Enable/Disable all 

Setting '1' Enable the corresponding interrupt

Setting '0' Disable the corresponding interrupt

Interrupt Priorities:

8051 has two levels of interrupt priorities: high or low. By assigning priorities, we can control the order in which multiple interrupts will be serviced. Priorities are set by bits in a special function register called IP, which is at the byte address B8H. This register is also bit addressable.

Interrupt Priority register (IP):

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
--	--	PT2	PS	PT1	PX1	PT0	PX0

Priority list:

1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt