Verilog Code To Realize All Logic Gates

Verilog Code To Realize All Logic Gates

AND Gate:

module andgate (a, b, y);

input a, b;

output y;

assign y = a & b;

endmodule

OR Gate:

module orgate (a, b, y);

input a, b;

output y;

assign y = a | b;

endmodule

NAND Gate:

module nandgate (a, b, y);

input a, b;

output y;

assign y = ~ (a & b);

endmodule

NOR Gate:

module norgate (a, b, y);

input a, b;

output y;

assign y = ~ (a | b);

endmodule

NOT Gate:

module inv (a, y);

input a;

output y;

assign y = ~ a ;

endmodule

EX-OR Gate:

module xorgate (a, b, y);

input a, b;

output y;

assign y =  (a ^ b);

endmodule

EX-NOR Gate:

module xnorgate (a, b, y);

input a, b;

output y;

assign y = ~ (a ^ b);

endmodule