Abstraction Levels in Verilog

Abstraction Levels in Verilog:

Verilog supports designing at many different levels of abstraction. Four of them are very important:

• Behavioral level
• Register-Transfer Level
• Gate Level
• Switch Level

Behavioral Level:

Verilog provides the designer the ability to describe the design functionality in an algorithmic manner. In other words the designer describes the behavior of the circuit. The abstraction in this modeling is as simple as writing the logic in C language. Verilog behavioral models contain procedural statements that control the simulation and manipulate variables of the data types. The activity starts at the control constructs initial and always. Each initial statement and each always statement starts a separate activity flow.

Procedural Assignments:

Procedural assignments update values of reg, integer, real, or time variables. The value placed on a variable will remain unchanged until another procedural assignment updates the variable with a different value.

Syntax:

   <assignment>
: : = < value > = < expression >

Blocking assignments:

Blocking assignment statements are executed in the order and they are specified in a sequential block. A blocking assignment will not block execution of statements that follow in a parallel block. The blocking assignments are made using the operator =.

Example:

initial
begin
          a = 5;
          b = #6 2;
          c = #8 3;
end

In the above example, ‘a’ is assigned value 5 at time 0, and ‘b’ is assigned value 2 at time 6, and ‘c’ is assigned value 3 at time 8.

Nonblocking Assignments:

Nonblocking assignment allows scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Non-blocking assignments are made using the operator <=.

Example:

initial
begin
          a <= 5;
          b <= #6 2;
          c <= #8 3;
 end

In the above example, ‘a’ is assigned value 5 at time 0, and ‘b’ is assigned value 2 at time 6, and ‘c’ is assigned value 3 at time 8 (because all the statements execution starts at time 0, as they are non-blocking assignments.

Initial Statement:

All statements inside an initial statement constitute an initial block. An initial block starts at time 0, and executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0.

Example:

If there is only one statement, we can write it as follows:

          initial

          count = 4’b0;

If there are more than statements are there to execute

           initial

           begin

                a=5;

                c=a;

           end     // both a and c will become 5.

Always Statement:

All behavioral statements inside an always statement constitute an always block. The always statement starts at time 0 and executes the statement in the always block continuously in a looping fashion.

Syntax:

                                always @ ( sencitivity_list )

                                                  statements;

Sensitivity list may contain signal names as follows:

                                always @ ( signal1 or signal2 )

                                                statement;                        

Without sensitivity list, always block will look like this:

                                                always

                                                #10 clk = ~clk;

This will toggle the signal clk for every 10 nanoseconds.

Register-Transfer Level:

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility; operations are scheduled to occur at certain times. Modern definition of a RTL code is "Any code that is synthesizable is called RTL code".

Example: RTL level 2:1 multiplexer

module mux2 (input a, b,              //data inputs
                    input select,           //select line
                    output z                 //output
                    );

always_comb begin

case (select)

                1’b0 : z = a;

                1’b1 : z = b;

               default : z = 1’bx;

endcase

end

endmodule

Gate Level:

At the next higher level of abstraction, design is carried out in terms of basic gates. All the basic gates are available as ready modules called “Primitives”. Each such primitive is defined in terms of its inputs and outputs. Primitives can be incorporated into design descriptions directly. Just as full physical hardware can be built using gates, the primitives can be used repeatedly and judiciously to build larger systems.

Basic Gates:

These implement the basic logic gates. They have one output and one or more inputs. In the gate instantiation syntax shown below, GATE stands for one of the keywords and, nand, or, nor, xor, xnor.

module all_gate ( a, b, y );

input a, b;

output [1:6] y;

assign y[1]= a & b;

assign y[2]= a | b;

assign y[3]= ~a ;

assign y[4]= ~(a & b);

assign y[5]= ~(a | b);

assign y[6]= a ^ b;

endmodule

Switch Level:

Verilog provides the ability to design at a MOS-transistor level. Design at this level is becoming rare with the increasing complexity of circuits (millions of transistors) and with the availability of sophisticated CAD tools. Modeling transistor networks at the switch-level more accurately represents their operation.

Verilog provides unidirectional and bidirectional primitives that you can use to model the switch networks.

The following are unidirectional primitives:

cmos    nmos     pmos    

The following are bidirectional primitives:

tran         tranif0       tranif1

MOS Switch:

Two types of MOS switches, nmos is used to model NMOS transistor, pmos is used to model PMOS transistors. The symbols for NMOS and PMOS switches are shown below.

Syntax:

nmos n1(out , data , control ) ;

pmos p1(out , data , control ) ;

CMOS Switch:

CMOS switches are declared with the keyword cmos. A CMOS device can be modeled with a NMOS and PMOS device. The symbol for a CMOS switch is shown below.

Syntax:

cmos c1(out , data , ncontrol , pcontrol ) ;

Example: (CMOS Inverter)

module cmos1 (out, in);

input in;

output out;

supply1 pwr;

supply0 gnd;

pmos u1(out, pwr, in);

nmos u2(out, gnd, in);

endmodule

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