How to write a VHDL code on Xilinx

keyword: VHDL, Xilinx tutorial

How to create a Project on Xilinx:

Creating a Project:

This gives an overview of how to create a new Xilinx project, add source files, synthesize, and implement your design.

1. Open up Xilinx project navigator

2. The open window has 4 panes:

1.    A source pane that shows the organization of the source files that make up your design. There are three tabs so you can view the functional modules or HDL libraries for your project or look at various snapshots of the project.

2.    A process pane that lists the various operations you can perform on a given object in the source pane.

3.    A log pane that displays the various messages from the currently running process.

4.    An editor pane where you can enter HDL code. Schematics are entered in a separate window.

To start your design:

Create a new project by selecting the File -> New Project item from the menu bar.

This brings up the New Project window where you can enter the location of your project files, project name, the target device for this design, and the tools used to synthesize logic from your source files.

Click on the “…” button next to the Project Location field and use the Browse for Folder window to select a folder where your project files will be stored. For this tutorial, you will store everything in the C:\tmp\fpga_designs folder. Click on the OK button after highlighting this folder. There can be no spaces in the path for the project. Files can be kept on your H:\ drive without a problem. This is better than putting it on the C:\ drive because where could lose your work.

Now give your project design the descriptive title of design1 by typing it into the Project name field. Then click on the Next button to continue creating this project.

Now you need to tell the software what FPGA you are going to use for your design. The device family, family member, package and speed grade for the FPGA if the model of out XSA Board is shown below. (configuration depends on the device)

XSA Board	Device Family	Device	Package	Speed Grade
XSA-200	Spartan2	xc2s200	fg256	-5

Click the Next button on the next window that appears. (You will create the VHDL source code at a later step.)

You have no existing source files to add to this project, so once again click the Next button.

The final screen shows the pertinent information for the new project. Click on the Finish button to complete the creation of the project.

Adding VHDL Source Files:

Now the Sources pane in the Project Navigator window contains two items:

1. A project object called design1.

2. A chip object called xc2s200-5fg256.

Once all the project set-up is complete, you can begin to actually design your ABCD circuit. Start by adding a VHDL file to the design1 project. Right-click on the xc2s200-5fg256, object in the Sources pane and select New Source … from the pop-up menu as shown below.

This causes a window to appear where you must select the type of source file you want to add. Since you are describing the ABCD with VHDL, highlight the VHDL Module item. Then type the name of the module, ABCD, into the File Name field and click on Next (VHDL is not a case sensitive language so you can use either lower or upper case).

The Define VHDL Source window now appears where you can declare the inputs and outputs to the ABCD circuit. You can declare your I/O here or just code it into the circuit. Click next to continue.

After clicking on Finish, the editor pane of the Project Navigator window displays a VHDL skeleton for your ABCD. (You can also see the ABCD.vhd file has been added to the Sources pane.) Now you must describe the behavior of the circuit using VHDL in the architecture section of the code. Once you have completed the description you need to check your code for syntactical errors.

Checking VHDL Code:

You can check for errors in your VHDL by highlighting the ABCD object in the Sources pane and then double-clicking on Check Syntax in the Process pane as shown below.

The syntax checking tool grinds away and then displays [not ok] the result in the process window. In this case, an error was found as indicated by the next to the Check Syntax process. But what is the error and where is it?

You can find the location of the error by scrolling the log pane at the bottom of the Project Navigator window until you find an error message. In this case, the error is located on line 25 and you can manually scroll there. You can also right-click on the error message in the log pane to go directly to the erroneous source.

You will know all coding errors are resolved when you double-click the Check Syntax process, it runs and then displays a [Ok].

Synthesizing Your Circuit:

Now that you have valid VHDL for your design, you need to convert it into a logic circuit. This is done by highlighting the ABCD object in the Sources pane and then double-clicking on the Synthesize-XST process. The synthesizer will read the VHDL code and transform it into a netlist of gates. This will take less than a minute. If no problems are detected, a check will appear next to the Synthesize process. You can double-click on the View Synthesis Report to see the various synthesizer options that were enabled and some device utilization and timing statistics for the synthesized design. You can also double-click on View RTL Schematic to see the schematic that was derived from the VHDL source code, but it’s not very interesting in this case.

keyword: VHDL, Xilinx tutorial