VHDL Tutorial-01

Keyword: HDL, VHDL

VHDL Tutorial-01

VHDL stands for VHSIC Hardware Description Language, and VHSIC in turn stands for Very High Speed Integrated Circuits. VHDL is an acronym for Very High Speed Integrated Circuit Hardware Description Language which is a programming language used to describe a logic circuit by function, data flow behavior, or structure.

VHDL is a programming language: although VHDL was not designed for writing general purpose programs, you can write any algorithm with the VHDL language. If you are able to write programs, you will find in VHDL features similar to those found in procedural languages such as C, Pascal or Ada. VHDL derives most of its syntax and semantics from Ada. Knowing Ada is an advantage for learning VHDL (it is an advantage in general as well).

However, VHDL was not designed as a general purpose language but as an HDL (hardware description language). As the name implies, VHDL aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an event-based timing model.

Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term simulation is often used instead of execution, with the same meaning. Like a program written in another hardware description language, a VHDL program can be transformed with a synthesis tool into a netlist, that is, a detailed gate-level implementation.

VHDL is one of the HDL languages available in the industry for designing the Hardware. VHDL allows us to design a Digital design at Behavior Level, Register Transfer Level (RTL), Gate level and at switch level. VHDL allows hardware designers to express their designs with behavioral constructs, deferring the details of implementation to a later stage of design in the final design.

Design Styles:

VHDL like other hardware description language (HDL) permits the designers to design a design in either Bottom-up or Top-down methodology.

Bottom-Up Design:

The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates ( Refer to the Digital Section for more details) With increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity.

Top-Down Design:

The desired design-style of all designers is the top-down design. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are mix of both the methods, implementing some key elements of both design styles.

VHDL TERMS:

The terms, which are of reference and common usage in VHDL programming, are as follows:

Entity: a hardware abstraction of digital system is called an entity. All designs are expressed in entities.

Architecture: All entities that can be simulated have architecture description. The architecture describes the behavior of entity.

Configuration: a configuration is used to bind a component instance to an entity –architecture pair. A configuration is like parts list for a design.

Package: A package is a collection of commonly used data types and subprograms used in a design. Package is just like a tool box that contains tools used to build designs. 

Bus: The term bus usually to mind a group of signals.

Attribute: An attribute is data attached to VHDL objects or predefined data above VHDL objects. For example: - Maximum operating temperature.

Process: A process is a basic unit of execution in VHDL source code. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.

Basic Structure of a VHDL file

A digital system in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity declaration and an architecture body. One can consider the entity declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in Figure 2.1 below. In a typical design there will be many such entities connected together to perform the desired function.

VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords and user-defined identifiers are case insensitive. Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and extra spaces. VHDL is a strongly typed language which implies that one has always to declare the type of every object that can have a value, such as signals, constants and variables.

Levels of abstraction

A digital system can be represented at different levels of abstraction. This keeps the description and design of complex systems manageable.

VHDL supports a design at many different levels of abstraction.

Three of them are very important

• Behavioral level
• Register – Transfer level
• Gate level

Behavioral level:

This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design.

Register-Transfer Level:

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility; operations are scheduled to occur at certain times. Modern definition of a RTL code is "Any code that is synthesizable is called RTL code".

Gate Level:

Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.

Keyword: HDL, VHDL